Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS
نویسندگان
چکیده
SOI (silicon-on-insulator) technology suffers from a number of floating body effects, most notably parasitic bipolar and history effects. These are influenced by the rapidly increasing gate tunneling current caused by an ultra-thin gate oxide, even at scaled VDDs [8]. This paper analyzes these effects in detail and proposes a number of novel circuit styles to minimize them. Simulation results are based on model parameters from an AMD 0.25 μm PD-SOI process.
منابع مشابه
Modeling of Gate Leakage, Floating Body Effect, and History Effect in 32nm HKMG PD-SOI CMOS
The High-K Metal Gate (HKMG) technology has become the keystone to reduce gate leakage and enable the continuous scaling of transistors towards 32nm node and beyond. However, the reduction of gate leakage in 32nm HKMG PD (Partially Depleted)-SOI (Silicon-On-Insulator) CMOS (Complementary Metal–Oxide–Semiconductor) inevitably changes the modeling methods for gate current, floating body effect, a...
متن کاملSoi Vs Cmos for Analog Circuit
This paper reviews the basic circuit issues of silicon-on-insulator (SOI) technology for metal-oxide-semiconductor (CMOS) circuits. The superior features of SOI in low power, high speed, high device density and the effect of floating body particularly in partial depletion (PD) SOI device are addressed. Analog and RF circuits are considered and their performances are compared with those reported...
متن کاملThe Industry Standard of SOI Technology From Process To Circuit Simulation
SOI technology for state of the art CMOS technology is rapidly approaching maturity. PD-SOI device design has the advantage of easier manufacturing but requires more sophisticated device and circuit design to reduce the effects of the floating-body. FD-SOI device design potentially has the advantage of no floating-body effects but requires very thin silicon films making manufacturing more chall...
متن کاملOutput-Conductance Transition-Free Method for Improving Radio-Frequency Linearity of SOI MOSFET Circuits
In this article, a novel concept is introduced to improve the radio frequency (RF) linearity of partially-depleted (PD) silicon-on-insulator (SOI) MOSFET circuits. The transition due to the non-zero body resistance (RBody) in output conductance of PD SOI devices leads to linearity degradation. A relation for RBody is defined to eliminate the transition and a method to obtain transition-free c...
متن کاملDesign of an Embedded Fully-Depleted SOI SRAM
We describe the design of an embedded 128-Kb Silicon-OnInsulator (SOI) CMOS SRAM, which is integrated alongside an array of pitch-matched processing elements to provide massively-parallel data processing within one integrated circuit. An experimental 0.25m fully-depleted SOI process was used. The design and layout of the SOI memory core and results from calibrated circuit simulations are presen...
متن کامل